VLSI 2017 Symposium  @ SmartTechCon2017

Welcome to VLSI 2017!

The International Symposium on Advances in VLSI Technology (VLSI 2017) is pleased to invite you to respond to our Call for Submissions for SmartTechCon2017, to be held from 17 - 19 August 2017 at the REVA University, Bangalore, India.

The usage of technology with daily life has reached a state where human life with semiconductors is intangible. The current cutting-edge technologies in VLSI provide the end-users a marvelous amount of applications, processing power and portability. The Electronics industry has achieved a phenomenal growth over the last few decades, mainly due to the rapid advances in large scale integration technologies and system design applications. With the advent of very large scale integration (VLSI) designs, the number of applications of integrated circuits (ICs) in high-performance computing, controls, telecommunications, image and video processing, and consumer electronics have been rising at a very fast pace. Symposium on Advances in VLSI Technology emphasize on providing a common platform for scientists and researchers to share recent developments.

Technical Committee

Dr. Rajashekhar C. Biradar, Professor and Director, School of ECE, REVA University, India. (Chair)
Dr. Venkat Shiva Reddy, REVA University, India
Dr. Bharathi S.H, REVA University, India
Dr. Basarkod, REVA University, India
Dr. Mrinal, REVA University, India
Dr. Geetha D, REVA University, India
Dr. Seshikala G, REVA University, India
Dr. Veena, REVA University, India
Dr. Manjula R. B., REVA University, India
Dr. Md.Riyaz Ahmed, REVA University, India
Dr. Manjunath Kounte, REVA University, India
Mr. K.M. Sudharshan, REVA University, India
Mr. S.N.Prasad, REVA University, India
Mr. Prashanth Joshi, REVA University, India
Mrs. Prameela N, REVA University, India
Mrs. SavithaP.R., REVA University, India
Mrs. NayanaD.K., REVA University, India
Mrs. Nirmala L., REVA University, India
Mr. NatrajUrs, REVA University, India
Mr. Raganna A., REVA University, India
Mrs. Raji C., REVA University, India
Mrs. Sowmiya Bharani, REVA University, India
Mr. Amrut Purohit, REVA University, India
Mrs. Neethu K. N., REVA University, India
Mrs. Dilna U., REVA University, India


Research articles are invited for the symposium on following topics but not limited to.

  • Low power devices
  • Modeling and Simulation
  • Multi-domain simulation
  • Device/circuit level variability models;
  • Reliability simulation
  • Logic and Physical synthesis
  • Place & Route, Clock Tree
  • Physical Verification
  • Signal integrity
  • Power analysis and integrity
  • Analog Mixed Signal IP
  • High-Speed interfaces
  • Low-power Analog and RF
  • Memory Design
  • Standard Cell Design
  • Low-power design
  • Thermal estimation and optimization
  • Power estimation methodologies
  • CAD tools
  • MEMS
  • CMOS sensors
  • CAD/EDA methodologies for nanotechnology
  • Nano-electronics and Nano-circuits
  • Nano-sensors, MEMS applications
  • Nano-assemblies and Devices
  • Carbon Nano-tubes based computing

Submission Guidelines

Submit your paper in IEEE format. Submitted work should be original and application oriented. Acceptance will be based on reviewer's comments that will address the strong and weak aspects with suggestions to improve the work.

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